I spoke too soon. Earlier today I outlined AMD’s roadmap for 2010 - 2011. In 2011 AMD will introduce two next-generation microarchitectures: Bulldozer for the high end desktop and server space and Bobcat for the price/power efficient ultra mobile market. I originally said that AMD wasn’t revealing any more about its next-gen architectures, but AMD just proved me wrong as they unveiled the first block diagrams of both cores.

First up, Bulldozer. I hinted at the architecture in this afternoon’s article:

“A major focus is going to be improving on one of AMD’s biggest weaknesses today: heavily threaded performance. Intel addresses it with Hyper Threading, AMD is throwing a bit more hardware at the problem. The dual integer clusters you may have heard of are the route AMD is taking...”

And here’s the block diagram:


Bulldozer: AMD's Latest Leap Forward, will it be another K8 to Intel's Sandy Bridge?

This is a single Bulldozer core, but notice that it has two independent integer clusters, each with its own L1 data cache. The single FP cluster shares the L1 cache of the two integer clusters.

Within each integer “core” are four pipelines, presumably half for ALUs and half for memory ops. That’s a narrower width than a single Phenom II core, but there are two integer clusters on a single Bulldozer core.

Bulldozer will also support AVX, hinted at by the two 128-bit FMAC units behind the FP scheduler. AMD is keeping the three level cache hierarchy of the current Phenom II architecture.

A single Bulldozer core will appear to the OS as two cores, just like a Hyper Threaded Core i7. The difference is that AMD is duplicating more hardware in enabling per-core multithreading. The integer resources are all doubled, including the schedulers and d-caches. It’s only the FP resources that are shared between the threads. The benefit is you get much better multithreaded integer performance, the downside is a larger core.

Doubling the integer resources but not the FP resources works even better when you look at AMD’s whole motivation behind Fusion. Much heavy FP work is expected to be moved to the GPU anyway, there’s little sense in duplicating FP hardware on the Bulldozer core when it will eventually have a fully capable GPU sitting on the same piece of silicon. While the first incarnation of Bulldozer, the Zambezi CPU, won't have an on-die GPU, presumably future APUs will use the new core. In those designs the Bulldozer cores and the GPU will most likely even share the L3 cache. It’s really a very elegant design and the basis for what AMD, Intel and NVIDIA have been talking about for years now. The CPU will do what it does best while the GPU does what it is good at.

Fascinating.

AMD’s Next-Generation Ultramobile Core: Bobcat

Next up is Bobcat:

AMD says that a single Bobcat is capable of scaling down to less than one watt of power. Typically a single microarchitecture is capable of efficiently scaling to an order of magnitude of TDP. If Bobcat can go low as 0.5W, the high end would be around 5W. If it’s closer to 1W at the low end then 10W would be the upper portion. Either way, it’s too low to compete in current mainstream notebooks, meaning that Bobcat is strictly a netbook/ultraportable core as AMD indicated in its slides. Eventually Bulldozer will probably scale down to take care of the mainstream mobile market.

AMD provided very little detail here other than it delivers 90% of today’s mainstream performance in less than half of the silicon area. If AMD views mainstream as an Athlon II X2, then Bobcat would deliver 90% of that performance in a die area of less than 60mm^2.

Clearly this is bigger than Atom, but that’s just a guess. Either way, the performance targets sound impressive. SSE1-3 are supported as well as hardware virtualization.

AMD wouldn’t tell me what process it would be made on but they did hint that Bobcat would be easily synthesizable. I take that to mean it will be built on a bulk 28nm process at Globalfoundries and not 32nm SOI.

Both of these cores will be out in 2011. We just need to make it through 2010 first.

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  • Etern205 - Thursday, November 12, 2009 - link

    A insider from Intel has leaked the design for their future cpu.
    Build on a 2nm process, quad qpi of 1.3TB/s, 24GB of L3 cache, operates at 1.6Ghz-5GHz, and comes in flavors of dual and all the way to 48 cores.

    The leaked memo states Intel with having much ran out of good codenames, they've all decided to agree to call this one TONKA. :P
    Reply
  • camylarde - Thursday, November 12, 2009 - link

    Ok, so I am planning to purchase that ATi 5870 next year after all. Its amazing what your 300 $ can do for the shape of a world ;-) Reply
  • fitten - Thursday, November 12, 2009 - link

    But I think it's risky... how much software is available to use the GPU and how much will be by then? Also, there are things like latency and such to consider when doing GPU offloading. So, doing something between no-floating point work and some amount of floating point work that amortizes the latencies and such for setting up the GPU to do the work, especially in a multithreaded program, will likely tank on it, I think (I don't know where the tradeoff is).

    As it is, you can write your programs to use the GPU using OpenCL/etc. but that has to load both your program and data onto the GPU to do the work then offload the data when done (the runtime may handle that stuff for you but it still takes time). What are the latencies involved with that (seriously, I don't know... haven't looked into it that deeply)?
    Reply
  • pcfxer - Thursday, November 12, 2009 - link

    Twinning the L1 cache, DAMN AMD beat me to that one and I'm a computing architecture MASTER!

    Note to AMD: Optimize the garbage out of the software side - micro-code, perhaps even hire on some GCC and PCC compiler teams to develop smarter linkers/cross-compilers.

    I don't know how Intel manages their microcode but I can assume that their software is more efficient considering the hardware similarities.
    Reply
  • JVLebbink - Thursday, November 12, 2009 - link

    With these two cores looking a lot the same (removing one integer cluster and not looking at the FPU) would that mean that Bulldozer also has only 90% of the single threaded integer performance of the current Phenom II?

    I wonder how they are going to make up for that with other enhancements?
    Reply
  • GaiaHunter - Friday, November 13, 2009 - link

    I don't think you can infer that. The pipelines are bound to be different and don't forget L3 cache and new set of instructions "Bulldozer" will have compared to Phenom II. Reply
  • GaiaHunter - Wednesday, November 11, 2009 - link

    There is been some discussion about this on the forums.

    When AMD says 4 Bulldozer cores, does it means 4Cores/8Threads or does it means a pair of bulldozer cores each with its "2 tightly linked together cores" able to do 4 threads?

    Thank you.
    Reply
  • Anand Lal Shimpi - Thursday, November 12, 2009 - link

    I believe it means 4 cores/8 threads, but I will ask AMD to confirm.

    Take care,
    Anand
    Reply
  • Anand Lal Shimpi - Thursday, November 12, 2009 - link

    Confirmed. 4 cores/8 threads, each Bulldozer core can handle two threads.

    Take care,
    Anand
    Reply
  • Eeqmcsq - Thursday, November 12, 2009 - link

    So does this mean the rumors of an 8 core Bulldozer are wrong? That they were referring to an 8 thread Bulldozer? Or is there really an 8 core/16 thread Bulldozer in the works? Reply

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