Yesterday AMD revealed that in 2014 it would begin production of its first ARMv8 based 64-bit Opteron CPUs. At the time we didn't know what core AMD would use, however today ARM helped fill in that blank for us with two new 64-bit core announcements: the ARM Cortex-A57 and Cortex-A53.

You may have heard of ARM's Cortex-A57 under the codename Atlas, while A53 was referred to internally as Apollo. The two are 64-bit successors to the Cortex A15 and A7, respectively. Similar to their 32-bit counterparts, the A57 and A53 can be used independently or in a big.LITTLE configuration. As a recap, big.LITTLE uses a combination of big (read: power hungry, high performance) and little (read: low power, lower performance) ARM cores on a single SoC. 

By ensuring that both the big and little cores support the same ISA, the OS can dynamically swap the cores in and out of the scheduling pool depending on the workload. For example, when playing a game or browsing the web on a smartphone, a pair of A57s could be active, delivering great performance at a high power penalty. On the other hand, while just navigating through your phone's UI or checking email a pair of A53s could deliver adequate performance while saving a lot of power. A hypothetical SoC with two Cortex A57s and two Cortex A53s would still only appear to the OS as a dual-core system, but it would alternate between performance levels depending on workload.

ARM's Cortex A57

Architecturally, the Cortex A57 is much like a tweaked Cortex A15 with 64-bit support. The CPU is still a 3-wide/3-issue machine with a 15+ stage pipeline. ARM has increased the width of NEON execution units in the Cortex A57 (128-bits wide now?) as well as enabled support for IEEE-754 DP FP. There have been some other minor pipeline enhancements as well. The end result is up to a 20 - 30% increase in performance over the Cortex A15 while running 32-bit code. Running 64-bit code you'll see an additional performance advantage as the 64-bit register file is far simplified compared to the 32-bit RF.

The Cortex A57 will support configurations of up to (and beyond) 16 cores for use in server environments. Based on ARM's presentation it looks like groups of four A57 cores will share a single L2 cache.


ARM's Cortex A53

Similarly, the Cortex A53 is a tweaked version of the Cortex A7 with 64-bit support. ARM didn't provide as many details here other than to confirm that we're still looking at a simple, in-order architecture with an 8 stage pipeline. The A53 can be used in server environments as well since it's ISA compatible with the A57.

ARM claims that on the same process node (32nm) the Cortex A53 is able to deliver the same performance as a Cortex A9 but at roughly 60% of the die area. The performance claims apply to both integer and floating point workloads. ARM tells me that it simply reduced a lot of the buffering and data structure size, while more efficiently improving performance. From looking at Apple's Swift it's very obvious that a lot can be done simply by improving the memory interface of ARM's Cortex A9. It's possible that ARM addressed that shortcoming while balancing out the gains by removing other performance enhancing elements of the core.

Both CPU cores are able to run 32-bit and 64-bit ARM code, as well as a mix of both so long as the OS is 64-bit.

Completed Cortex A57 and A53 core designs will be delivered to partners (including AMD and Samsung) by the middle of next year. Silicon based on these cores should be ready by late 2013/early 2014, with production following 6 - 12 months after that. AMD claimed it would have an ARMv8 based Opteron in production in 2014, which seems possible (although aggressive) based on what ARM told me.

ARM expects the first designs to appear at 28nm and 20nm. There's an obvious path to 14nm as well.

It's interesting to note ARM's commitment to big.LITTLE as a strategy for pushing mobile SoC performance forward. I'm curious to see how the first A15/A7 designs work out. It's also good to see ARM not letting up on pushing its architectures forward.

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  • B1gBOY - Tuesday, October 30, 2012 - link

    Not only Intel. If you think about it, Anandtech EIC must be sweating too...You know what i mean... Reply
  • bengildenstein - Tuesday, October 30, 2012 - link

    When hearing "3x performance at 0.25 the size," it feels eerily close to the same tech strategy as Imaginations Meta CPU core. For the uninitiated, the Meta core eschews out-of-order operations, and instead adopts an in-order multi-threaded approach which gives a significant bump in performance for cache-miss scenarios when spread over multiple cores, but is radically more simple than traditional ooo cores (hence the reduction in die space). Reply
  • blanarahul - Tuesday, October 30, 2012 - link

    Now AMD's announcement makes sense. Reply
  • blanarahul - Tuesday, October 30, 2012 - link

    Hmmmmm. Now we all know what Galaxy S5 will have. And what Qualcomm is working on (Snapdragon S5). Reply
  • blanarahul - Tuesday, October 30, 2012 - link

    (Sorry for repeated comments)

    Look at the second picture of this post (big.LITTLE diagrams).
    In the Superphone part of the diagram, 2 Cortex A57s are there and 4 Cortex A53s are there. What would be the possible use of this? Wouldn't it be hard to implement as it utilizes 2.4 configuration?
    Reply
  • Symmetry81 - Tuesday, October 30, 2012 - link

    Not really. The switching is done by the operating system, and with a 2.4 you just reserve two of the little cores for always running light tasks, and switch your other two sets of threads between the big and little cores. Reply
  • dylan522p - Tuesday, April 09, 2013 - link

    Qualcomm is on S200, S400, S600(S4/ONE), S800(Q4). They dropped the S4 naming scheme. Reply
  • iwod - Tuesday, October 30, 2012 - link

    A hypothetical SoC with two Cortex A57s and two Cortex A53s would still only appear to the OS as a dual-core system, but it would alternate between performance levels depending on workload.

    which means you cant use alll 4 core at the same time?
    Reply
  • Krysto - Tuesday, October 30, 2012 - link

    You might be able to, but not sure if with A15 and A7. ARM hinted that they want to use all cores through heterogenous computing, but I'm not sure if that will be available since next year. Might be available by A57/A53. Reply
  • Symmetry81 - Tuesday, October 30, 2012 - link

    Some people are working on a way to do that in Linux, but are having a hard time. So it might be possible, but it's fighting against the design. Even if you do manage to do it you won't be able to use the special hardware acceleration for switching execution from the A7 to the A15 and vice versa, though. Reply

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