At CES this year Samsung introduced the oddly named Exynos 5 Octa SoC, one of the first Cortex A15 SoCs to implement ARM's big.LITTLE architecture. Widely expected to be used in the upcoming Galaxy S 4, the Exynos 5 Octa integrates 4 ARM Cortex A7 cores and 4 ARM Cortex A15 cores on a single 28nm LP HK+MG die made at Samsung's own foundry. As we later discovered, the Exynos 5 Octa abandons ARM's Mali GPU for Imagination's PowerVR SGX 544MP3, which should give it GPU performance somewhere between an iPad 3 and iPad 4.

The quad-core A7 can run at between 200MHz and 1.2GHz, while the quad-core A15 can run at a range of 200MHz to 1.8GHz. Each core can be power gated independently. The idea is that most workloads will run on the quad-core A7, with your OS hot plugging additional cores as performance demands increase. After a certain point however, the platform will power down the A7s and start switching over to the A15s. Both SoCs implement the same revision of the ARM ISA, enabling seamless switching between cores. While it's possible for you to use both in parallel, initial software implementations will likely just allow you to run on the A7 or A15 clusters and switch based on performance requirements.

What's most interesting about Samsung's ISSCC presentation is we finally have some hard power and area data comparing the Cortex A15 to the Cortex A7. The table above puts it into numbers. The quad-core A15 cluster occupies 5x the area of the quad-core A7 cluster, and consumes nearly 6x the power in the worst case scenario. The area difference is artificially inflated by the fact that the A15 cluster has an L2 cache that's 4x the size of the A7 cluster, but looking at the die photo below you can get a good feel for just how much bigger the A15 cores are themselves:

In its ISSCC presentation, Samsung stressed the value of its custom libraries, timing tweaks and process technology selection in bringing the Exynos 5 Octa to market. Samsung is definitely marching towards being a real player in the SoC space and not just another ARM licensee.

The chart below is one of the most interesting, it shows the relationship between small integer code performance and power consumption on the Cortex A7 and A15 clusters. Before switching from the little CPU to the big one, power consumption is actually quite reasonable - south of 1W and what you'd expect for a smartphone or low power tablet SoC. At the lower end of the performance curve for the big CPU things aren't too bad either, but once you start ramping up clock speed and core count power scales linearly. Based on this graph, it looks like it takes more than 3x the power to get 2x the performance of the A7 cluster using the Cortex A15s.

 

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  • Wilco1 - Wednesday, February 20, 2013 - link

    The L2 caches have a special port to allow cachelines to be swapped directly. When both caches are powered up, coherency is maintained between them. Reply
  • DigitalFreak - Wednesday, February 20, 2013 - link

    We have an armchair engineer in 'da house! Reply
  • xaml - Saturday, February 23, 2013 - link

    An ARM-chair engineer... ;) Reply
  • Wilco1 - Wednesday, February 20, 2013 - link

    Ever heard of Google?

    http://samsung.com/global/business/semiconductor/m...
    Reply
  • tuxRoller - Wednesday, February 20, 2013 - link

    It depends on what is handling the switching.
    These initial implementations are using a cpufreq driver with internel core switching being moved from the hypervisor to the kernel in order to switch between pairs (as illustrated above, the heterogeneous mode will come after a good solution is found for the scheduler). The switching times aren't bad b/c you have cache coherency (not shown above) and thus you only need to transfer the active register states.

    http://lwn.net/Articles/481055/
    http://lwn.net/Articles/501501/#Add%20Minimal%20Su...
    Reply
  • amdwilliam1985 - Wednesday, February 20, 2013 - link

    I can't wait to see benchmarks on these.

    "While it's possible for you to use both in parallel, initial software implementations will likely just allow you to run on the A7 or A15 clusters and switch based on performance requirements."
    -Imagine future projects such as OUYA based on this baby with all cores enabled :)
    This will be a perfect HTPC.

    Intel better be prepare, time is ticking. Seems like every generation, ARM cpu takes a big jump in performance.
    Reply
  • Jinxed_07 - Wednesday, February 20, 2013 - link

    There's a difference between a more powerful CPU and one that simply has more cores slapped on. If ARM really had a more powerful CPU, then this architecture would only have one smaller CPU that was able to run everything while consuming less eneregy, rather then needing two in order to save energy.
    Futhermore, if Intel should be afraid of ARM, then they should be afraid of AMD for making an 8-core processor that outperforms a 4-core processor by a bit.
    Reply
  • flyingpants - Wednesday, February 20, 2013 - link

    Hello. In the first chart, it says both quad core CPUs are ARM 7. No mention of ARM 15. Is this correct? Reply
  • Cow86 - Wednesday, February 20, 2013 - link

    I'm afraid you are confused in this case...that is the architecture of the cores, being ARM v7...all Cortex cores use this architecture, the A5, A7, A8, A9 and A15...so it is correct :) The left column in that table is the A15, the right is the A7. Reply
  • pyaganti - Thursday, February 21, 2013 - link

    Any idea why samsung is using A7 for little instead of A5? If A7 and A5 are both ARM v7 archietecture, it makes more sense if they use A5 instead of A7. Beacuse A5 is low power core than A7 and thats the main concept of little core right? Reply

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