When Intel released the Slot-1 Pentium II in 1997, the market marveled at its size and criticized Intel for taking a step in the wrong direction. While the rest of the CPU market was happily resting on the Socket-7 platform, Intel was pushing their customers towards a $1000 chip that could fit into no socket known to man.

From Intel’s perspective, the move was necessary. The presence of the L2 cache on the motherboard was a bottleneck that the market knew well; unfortunately, no viable solution to the problem was at hand, so things continued the way they had been.

Intel’s first attempt at removing the bottleneck was to place the L2 cache in a package alongside the CPU that operated at the speed of the CPU. Keep in mind that this did not mean placing the L2 cache on the same die as the CPU, rather placing it near the die in a completely separate package. The name of this creation was the Pentium Pro.

At its peak, the Pentium Pro was manufactured on a 0.35-micron process that simply did not allow for a full 256KB, 512KB, or 1MB L2 cache on its die. So the package was separate from the core, but before the processor could be tested and put through Intel’s rigorous quality control tests, the two packages had to be joined and thus a full processor produced. There was no way of testing the CPU independently from the L2 cache, so if there was a problem in either of the two packages, the entire CPU had to be thrown away.

The second attempt was made in 1997, as we said earlier, with the release of the Pentium II, the first Intel CPU to make use of a Single Edge Contact Connector (SECC) or Slot-1 interface. The SECC card featured 512KB of L2 cache on the card itself, which could be manufactured by any outside source and still allowed the CPU to be tested prior to assembly. This card solved some of the problems posed by the Pentium Pro, but it also created new problems, such as those associated with the card that the actual Pentium II CPU was mounted on. The idea of placing the L2 cache on the die of the processor was still not within Intel’s reach. However, it did fall within their reach the following year, with the release of the Celeron A processor.

At what can be arguably considered to be the peak of Intel’s 0.25-micron production, the Celeron A was the first Intel CPU to feature L2 cache on the processor’s die itself. This means that the L2 cache is a physical part of the processor’s core and not contained within a separate package. The Celeron became the first desktop Intel processor since the Pentium II that had no use for the SECC processor card it was placed on. We were told that we wouldn’t see the next CPU that fit this description until Intel made the move to 0.18-micron.

The 0.18-micron fabrication process is finally upon us. The smaller fabrication process means that CPUs get faster, prices get lower and chips get tinier. The latter is the point that we address today, as we take a look at Intel’s Flip Chip PGA Pentium III E. The term Flip Chip is just a term that describes the Socket-370 version of the Organic Land Grid Array (OLGA) core that allows the heatsink to be attached directly to the die.

As we know from our review of the Pentium III E, otherwise known as the Coppermine processor, the ~29 million transistor CPU is the first desktop processor from Intel manufactured on the 0.18-micron process. The die features a full 256KB of L2 cache which makes the SECC-2 processor card a waste of space and more importantly, a waste of money. Since Intel already has a socketed platform ready (Socket-370, used by the Celeron CPUs), it would make perfect sense for Intel to make the transition to a socketed platform for their new Pentium III E. And thus we have the creation of the Socket-370 Pentium III E processor, or officially, the FC-PGA Pentium III E.

The Chip

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