Rambus DRAM Part 2: Performance

Imagine for a minute what would happen if the line representing the BX/PC100 or Apollo Pro 133A/PC133 configurations was not effected by the 800MB/s or 1.06GB/s peak bandwidth limitations of the respective memory types.  Instead, imagine the lines having a peak bandwidth equal to that of RDRAM, 1.6GB/s or possibly even greater than that. 

While these performance lines aren't present on that particular graph, you would be imagining the latency versus bandwidth utilization graph of DDR SDRAM.  This would be a lower latency solution than RDRAM on an 820 chipset and would feature a much lower cost premium than RDRAM since the expected price point of DDR SDRAM is supposed to be only a few percent more expensive than SDRAM, which is much lower than the 20%+ price point that RDRAM will have when DDR SDRAM becomes a readily available option in the market later this year.

This is why we made it a point to mention that, in spite of the lower pin count of RDRAM, currently DDR SDRAM is the way to go because it offers all of the bandwidth benefits of RDRAM with the low latency of SDRAM that we're used to, without the price premium of RDRAM. 

In the future, when the pin count of 64-bit DDR SDRAM becomes an issue and adding a second channel isn't exactly feasible, then RDRAM will perhaps be primed and ready to take over, but not until then.  That was the intended aim of our first article on Rambus.