Intel 845 Chipset Review & Motherboard Roundup: September 2001

Deeper Buffers & Write Cache: Perfect for DDR

The i845 Memory & Controller Hub (MCH) is Intel's first 0.18-micron MCH.  Even the recent i850 MCH was built on a 0.25-micron process like the earlier 815 and 820 chipsets.  The fact that the MCH is a 0.18-micron solution means lower manufacturing costs as well as a very small die.  As you can see from the below picture, the MCH itself is the smallest we've ever seen out of a current generation chipset.

The watermark of a US dime gives you an idea of how small the core of the chipset is.

The 845 MCH is also Intel's first chipset to use a Flip Chip BGA packaging for the chip itself.  This improves heat conductivity between the MCH and its heatsink which is required for proper operation.  With such a small die surface area, a good heatsink and mounting mechanism is necessary to conduct heat away from the chip.  The MCH doesn't get excessively hot, but a heatsink is still required.

Had the 845 been produced on a 0.25-micron process, it would be almost 50% larger than its current size; the savings offered by Intel's very mature and very advanced 0.18-micron process are evident in some of the features that were included into the MCH.

The first major improvement is the inclusion of a write cache.  This is the first SDRAM chipset from Intel to employ a write cache on the MCH itself; the i850 and i860 both had similar write caches.  It should be obvious by now that today's CPUs run much faster than the memory they have to store data in.  When the Pentium 4, for example, goes to write data to memory, it must send the write command and data through the FSB, into the MCH, out through the memory bus and, finally, to the memory itself.  In order to sustain maximum bus efficiency, these writes would normally be buffered so that the Pentium 4 could go back to work as soon as possible.  The next step beyond a simple buffer is an intelligent memory storage that would actually cache the writes and act as a very small L3 cache on the MCH itself.  Now, we're still not dealing with a full fledged read/write L3 cache on the MCH itself, but we're getting there.  This is made possible by the small 0.18-micron die.  It wouldn't be too surprising to see the transition to 0.13-micron MCH/North Bridges met with much larger read and write caches, eventually bringing us to L3 caches on the chipset for mainstream solutions.

The second major feature of the 845 is its very deep buffers.  We praised the P4X266 chipset for being buffered deeply enough to take advantage of the greater transfer rates that DDR SDRAM offers over regular SDRAM, which VIA was used to implementing on chipsets; the i845 is actually buffered even deeper.  The deeper your buffers, the higher your sustained memory bandwidth can be.  This comes courtesy of the maximum In Order Queue (IOQ) depth level of 12 on the 845 vs. 8 on the i850 and on the P4X266. 

Before you get too excited about these two features, you must realize that, although they help to make very efficient use of the available memory bandwidth, they don't get around the fact that the 845's currently only has PC133 SDRAM at its disposal.  So although the combination of an intelligent write cache and deeper buffers gives the 845 the leg up on the P4X266 in terms of efficient bandwidth usage, the P4X266 still has twice as much bandwidth at its disposal.  Then, why on earth would Intel outfit the i845 with such an advanced MCH? 

For one, the Pentium 4 at 1.5GHz and above needs at least 1.5GB/s of memory bandwidth to perform close to its peak.  Unfortunately, even at 100% bus utilization (not real world by any means) PC133 SDRAM can only provide 1.06GB/s of memory bandwidth.

The second possibility would be that the i845 was to pave the way for an extraordinarily high performing DDR SDRAM solution.  Based on the current specifications of the 845, it would not be surprising if a DDR266 (PC2100) version of the chipset outperformed the i850 with today's Pentium 4s.  We have already seen that the P4X266 can come within a few percentage points of the i850; even deeper buffering and an intelligent write cache could place DDR a bit outside of Intel's desired positioning for it.  Fortunately, for Intel (but unfortunately for the consumer), the 845-D (DDR) is set to debut with only DDR200 SDRAM and not DDR266. Update: Intel has confirmed that in Q1-2002 they will debut with both DDR200 and DDR266 support.