Inside ATI & NVIDIA: How they make frames fly

Inside ATI - Designing a Chip

We've often been asked how exactly these graphics giants go about doing what they do, and that's exactly what we asked an ASIC engineer at ATI to help us explain.

The first step in GPU design is of course, marketing; a spot will be defined in the market, where the product will end up being aimed at. A document describing this gets served to a lead architect where details such as costs, schedules and resources required are discussed.

The cost limitations also help determine figures like transistor counts; at this stage the target manufacturing process is also chosen depending on a number of factors. As you can expect the manufacturing process (e.g. 0.15-micron, 0.13-micron, 90nm, etc…) contributes to the cost structure of the chip and imposes die sizes/transistor count limitations as well. What's important to note is that the target manufacturing process is decided upon at the very start of the design cycle based on estimates of where the foundry (the people that actually manufacture the chip - e.g. TSMC) will be at by the completion date. If this estimate is off, which was the case with NVIDIA's NV30 design, then the GPU will be inevitably delayed. Once a manufacturing process is decided upon, it is extremely difficult to, months later, go back and attempt to revise the design for a different process.

Discussions will continue between the designers and the marketing team for a matter of weeks. The process works much like a loop, with the designers revising documents sent to them by the marketing folks and so on and so forth.

Once a product cost and schedule is decided upon, it's time to start building the architecture. A team of engineers is roundup up and they start defining the features of the GPU, who will be working on them as well as defining the design schedule (e.g. Team 1 - have antialiasing unit completed in three weeks). Before we get to the actual designing you have to understand a bit of how you actually make a chip.

These days, chip architecting has been made infinitely easier through the advent of Hardware Description Languages (HDLs). A HDL, as the name implies, is a type of programming language that effectively describes hardware. Using a HDL such as Verilog or VHDL (two common HDLs), a designer would write code that is translated by a synthesizer into a netlist or schematic that can be used to produce a chip from. Thus when designing actually begins, there's a bit of circuit diagramming but mostly a lot of code-writing. Keep in mind that programming in these HDLs is absolutely nothing like programming in C or C++. While the code may look very similar to C, the actual functionality is very different. Let's take a very basic example from Verilog:

always@(posedge clock)
Q <= D;

The above code executes whenever there's a rising edge on the clock; when it does execute, the input signal 'D' is stored in 'Q'. We've effectively designed a very basic form of memory using a storage element known as a flip-flop. A synthesizer would take this code and produce a circuit based on the hardware that this code describes; in this case it would produce a storage element that would retain the value of its input.

Using their skills, the team of engineers would then code and design the chip and all of its units in a HDL, like Verilog, for around 3 to 4 months (depending on the scale of the project). During these months of coding, all of the features decided upon earlier are now implemented into the actual chip itself.

After the design is completed the next few months are spent in verification. The process of verification is critical to meeting production schedules because it helps get rid of problems before the chip is actually sent to the foundry for production. If a chip comes back from the foundry and it turns out that the design doesn't work as planned, then you've not only wasted a good deal of time but also an incredible amount of money.

Part of the verification process entails basic functionality tests to make sure that all of the gates within the chip work properly. Workloads are also simulated to make sure that the gates not only work but they also work as expected. Some of these tests are also conducted through the HDL itself by writing programs to test the hardware (sort of simulating a tester as well as the chip itself).

At this point one team will branch off and begin some static timing analysis to make sure that the chip will be able to meet clock speed goals. Remember that even at this point there is no physical "chip" just a simulation. While all of this is happening, a team of analog engineers is working on the memories, power circuitry, etc… Analog design and engineering is a very complex and dramatically different beast from the digital logic that we've been talking about until this point, there's a strong focus on understanding the elements of complex numbers, differential equations and signal analysis. The analog portion of the equation cannot be ignored as it's a very important part of the GPU design and manufacturing process; luckily the digital designers don't have to mess with it too much.