Typical branches have one of two options: either don’t take the branch, or go to the target instruction and begin executing code there:

A Typical Branch

...
Line 24: if (a = b)
Line 25:
execute this code;
Line 26: otherwise
Line 27: go to line 406;
...

Most branches have two options - don't take the branch or go to the target and start executing there

There is a third type of branch – called an indirect branch – that complicates predictions a bit more. Instead of telling the CPU where to go if the branch is taken, an indirect branch will tell the CPU to look at an address in a register/main memory that will contain the location of the instruction that the CPU should branch to. An indirect branch predictor, originally introduced in the Pentium M (Banias), has been included in Prescott to predict these types of branches.

An Indirect Branch

...
Line 113: if (z < 2)
Line 114: execute this code;
Line 115: otherwise
Line 116: go to memory location F and retreive the address of where to start executing

...

Conventionally, you predict an indirect branch somewhat haphazardly by telling the CPU to go to where most instructions of the program end up being located. It’s sort of like needing to ask your boss what he wants you to do, but instead of asking just walking into the computer lab because that’s where most of your work ends up being anyways. This method of indirect branch prediction ends up working well for a lot of cases, but not all. Prescott’s indirect branch predictor features algorithms to handle these cases, although the exact details of the algorithms are not publicly available. The fact that the Prescott team borrowed this idea from the Pentium M team is a further testament to the impressive amount of work that went into the Pentium M, and what continues to make it one of Intel’s best designed chips of all time.

Prescott’s indirect branch predictor is almost directly responsible for the 55% decrease in mispredicted branches in the 253.perlbmk SPEC CPU2000 test. Here’s what the test does:

253.perlbmk is a cut-down version of Perl v5.005_03, the popular scripting language. SPEC's version of Perl has had most of OS-specific features removed. In addition to the core Perl interpreter, several third-party modules are used: MD5 v1.7, MHonArc v2.3.3, IO-stringy v1.205, MailTools v1.11, TimeDate v1.08

The reference workload for 253.perlbmk consists of four scripts:

The primary component of the workload is the freeware email-to-HTML converter MHonArc. Email messages are generated from a set of random components and converted to HTML. In addition to MHonArc, which was lightly patched to avoid file I/O, this component also uses several standard modules from the CPAN (Comprehensive Perl Archive Network).

Another script (which also uses the mail generator for convienience) excercises a slightly-modified version of the 'specdiff' script, which is a part of the CPU2000 tool suite.

The third script finds perfect numbers using the standard iterative algorithm. Both native integers and the Math::BigInt module are used.
Finally, the fourth script tests only that the psuedo-random numbers are coming out in the expected order, and does not really contribute very much to the overall runtime.

The training workload is similar, but not identical, to the reference workload. The test workload consists of the non-system-specific parts of the acutal Perl 5.005_03 test harness.

In the case of the mail-based benchmarks, a line with salient characteristics (number of header lines, number of body lines, etc) is output for each message generated.

During processing, MD5 hashes of the contents of output "files" (in memory) are computed and output.

For the perfect number finder, the operating mode (BigInt or native) is output, along with intermediate progress and, of course, the perfect numbers.
Output for the random number check is simply every 1000th random number generated.

As you can see, the performance improvement is in a real-world algorithm. As is commonplace for microprocessor designers to do, Intel measured the effectiveness of Prescott’s branch prediction enhancements in SPEC and came up with an overall reduction in mispredicted branches of about 13%:

Percentage Reduction in Mispredicted Branches for Prescott over Northwood (higher is better)
164.gzip
1.94%
175.vpr
8.33%
176.gcc
17.65%
181.mcf
9.63%
186.crafty
4.17%
197.parser
17.92%
252.eon
11.36%
253.perlbmk
54.84%
254.gap
27.27%
255.vortex
-12.50%
256.bzip2
5.88%
300.twolf
6.82%
Overall
12.78%

The improvements seen above aren’t bad at all, however remember that this sort of a reduction is necessary in order to make up for the fact that we’re now dealing with a 55% longer pipeline with Prescott.

The areas that received the largest improvement (> 10% fewer mispredicted branches) were in 176.gcc, 197.parser, 252.eon, 253.perlbmk and 254.gap. The 176.gcc test is a compiler test, which the Pentium 4 has clearly lagged behind the Athlon 64 in. 197.parser is a word processing test, also an area where the Pentium 4 has done poorly in the past thanks to branch-happy integer code. 252.eon is a ray tracer, and we already know about 253.perlbmk; improvements in 254.gap could have positive ramifications for Prescott’s performance in HPC applications as it simulates performance in math intensive distributed data computation.

The benefit of improvements under the hood like the branch prediction algorithms we’ve discussed here is that they are taken advantage of on present-day software, with no recompiling and no patches. Keep this in mind when we investigate performance later on.

We’ll close this section off with another interesting fact – although Prescott features a lot of new improvements, there are other improvements included in Prescott that were only introduced in later revisions of the Northwood core. Not all Northwood cores are created equal, but all of the enhancements present in the first Hyper Threading enabled Northwoods are also featured in Prescott.

Prescott's New Crystal Ball: Branch Predictor Improvements An Impatient Prescott: Scheduler Improvements
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  • Jeff7181 - Sunday, February 1, 2004 - link

    I'm going to go out on a limb here and say 2004 is the year of the Athlon-64 and Intel will take a back seat this year unless their new socket will help increase clock speeds. When AMD makes the transition to 90nm I think you'll see a jump in clock speed from them too... and I'm willing to bet their current 130nm processors will scale to 2.6 or 2.8 Ghz if they want to put the effort into it before switching to 90nm.

    Intel better hope people adopt SSE3 in favor of AMD-64 otherwise they're going to lose the majority of the benchmark tests.

    On second thought... the real question is how high will Prescott scale... will we really see 4.0 Ghz by the end of the year? Will performance scale as well as it does with the Athlon-64?

    Right now, looking at the Prescott, the best I can say for it is "huh, 31 stages in the pipeline and they didn't lose too much performance, neat."
  • Barkuti - Sunday, February 1, 2004 - link

    Check out the article at xbitlabs:

    http://www.xbitlabs.com/articles/cpu/display/presc...

    Less technical but with a wider set of tests.
  • Stlr22 - Sunday, February 1, 2004 - link

    ;-)
  • Stlr22 - Sunday, February 1, 2004 - link

    ((((((((((((((CRAMITPAL))))))))))))))))

    Listen,I just want you to know that everything will be alright. Really, life isn't all that bad buddy. It's not good to keep so much hate inside. It's very unhealthy. We are all family here at the Anandtech forums and we care about you. If you ever need to sit down and talk, I'm ll ears pal. So that your brother doesn't feel left out, here's a hug for him aswell.......


    (((((((((((((AMDjihad)))))))))))))
  • KF - Sunday, February 1, 2004 - link

    Yeah, the Inquirer was right about 30 stages. Maybe I should start reading it! However I did read the one where the news linked to an article purporting that an Inquirer reporter had bumped into a person who had overheard an Intel executive say Prescott was 64 bit. Maybe Derek and Anand didn't have the space to squeeze that tiny detail into the review.

    I saw a paper on the Intel site a while ago, seemingly intended for some professional jounal, the premise of which was that it is ALWAYS preferable to make the pipeline longer, no matter how long, while using techniques to reduce the penalties. Like, 100 stages would be a good thing. Right then I knew what one team at Intel was up to. The fact that they didn't explain any new penalty reduction techniques only made it all the more sure what Intel had in the works (otherwise why write the paper?), and that they had the techniques worked out, but still under wraps.
  • ianwhthse - Sunday, February 1, 2004 - link

    Err.. *Cramitpal

    Sorry about that. My mind is wandering.
  • ianwhthse - Sunday, February 1, 2004 - link

    Did we actually just get 26 good posts in before crumpet showed up?
  • FiberOptik - Sunday, February 1, 2004 - link

    I like the part about the new shift/rotate unit on the CPU. Does this mean that prescott will be noticeably faster for the RC5 project? Athlon's usually mop the floor with whatever the Northwood can pump out.
  • eBauer - Sunday, February 1, 2004 - link

    "Botmatch has bots (AI) playing, shooting, running, etc. (deathmatch) while Flyby does not. The number that you should be most interested in is the Botmatch scores."

    No, I am talking about the botmatch scores from previous articles. Well aware of the difference between flyby and botmatch. http://www.anandtech.com/cpu/showdoc.html?i=1946&a... In that article, all CPU's had about 10 more fps than the CPU's in the prescott article.




  • AnonymouseUser - Sunday, February 1, 2004 - link

    "I am curious as to why the UT2k3 botmatch scores dropped on all CPU's... Different map?"

    Botmatch has bots (AI) playing, shooting, running, etc. (deathmatch) while Flyby does not. The number that you should be most interested in is the Botmatch scores.

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