Understanding the Cell Microprocessor
by Anand Lal Shimpi on March 17, 2005 12:05 AM EST- Posted in
- CPUs
Three very interesting things happened over the past couple of weeks here at AnandTech:
- Intel’s Spring IDF 2005 turned out to be a multi-core CPU festival, with Intel being even more open than ever before about future plans for their multi-core microprocessor architectures. Intel has over 10 multi-core CPU designs in the works, and they made that very clear at IDF.
- At GDC 2005, AGEIA announced that they had developed a Physics Processing Unit (PPU) that could be used to enable extremely realistic physics and artificial intelligence models.
- Johan De Gelas went one step further in his quest for more processing power earlier this week to find that there’s quite a lot of potential for multi-core CPUs in the gaming market, at the expense of increasing development times.
Cell, at a high level, isn’t too difficult to understand; it’s how the designers got there that is most intriguing. It’s the design decisions and building blocks of Cell that we’ll focus on here in this article, with an end goal of understanding why Cell was designed the way it was.
A joint venture between IBM, Sony and Toshiba, the Cell microprocessor is the heart and soul of Sony’s upcoming Playstation 3. However, this time around, Sony and Toshiba are planning to use Cell (or parts of it) in everything from consumer electronics to servers and workstations. If you don’t already have the impression, publicly, Cell has been given some very high aspirations as a microprocessor, especially a non-x86 microprocessor.
Facebook
Twitter
RSS
70 Comments
View All Comments
faboloso112 - Thursday, March 17, 2005 - link
ahh i love bedtime stories!great read...VERY informative!
ksherman - Thursday, March 17, 2005 - link
sweet article! way over my head, but there were some parts that were dropped down to my level of understanding. Leave it to anand to tell the real story. It will be interesting to see how willing some companies will be to accomidate Sony's ratical processor... bu tas long as theirs money... Do you think that it is possible to (down the road) flop a x86 chip in place of the PPE? wouldn't hat make the Cell compatible with the current processing standards?ProviaFan - Thursday, March 17, 2005 - link
Describing this as a "sit down read" type of article makes me want to print it out to put it in the magazine rack, because I don't have a laptop + 802.11g to peruse AnandTech while I'm, er... ;)xsilver - Thursday, March 17, 2005 - link
nice, definitley one of those "sit down reads".... some serious shiznit ;)cosmotic - Thursday, March 17, 2005 - link
OMG! FIRST POST LOL ROFL LMAO OMG!!! LOOK WHOS COOL!!!Fricardo - Thursday, March 17, 2005 - link
Finally! Thanks guys.Bawl - Saturday, January 25, 2014 - link
I just love this deep analysis of one of the most mist-understanding processor of the last decade.Too bad that after spending more than a half-of-billion dollars, SonyThoshibaIBM didn't release the presumably outstanding CellTwo.
Ferrx - Sunday, December 20, 2015 - link
Hi, can you help me to understand this ? I don't understand at all about these._______ _________ ______
|Decode| | Execute | | Write |
----------- ---------------- -----------
| I1 | I2 | | | | | | | |
| I3 | I4 | | I1 | I2 | | | | |
| I3 | I4 | | I1 | | | | I2 | |
| | I4 | | | | | | I1 | I3 |
| I5 | I6 | | | | I4 | | I4 | |
| | I6 | | | I5 | | | I5 | |
| | | | | I6 | | | I6 | |
_______ _________ ______
In "Decode", each row has 2 columns. What do First and Second Column mean ?
same as "Write"
And in "Execute, each row has 3 columns. What do First, Second and Third column mean ?
And how is the process ? (The current table is about "In-Order Issue with Out-of-Order Completion").
I've read it many times, in the "Instruction Level Parallelism". But I still don't have any idea about it.
Ferrx - Sunday, December 20, 2015 - link
Hi, can you help me to understand this ? I don't understand at all about these._______ _________ ______
|Decode| | Execute | | Write |
----------- ---------------- -----------
| I1 | I2 | | | | | | | |
| I3 | I4 | | I1 | I2 | | | | |
| I3 | I4 | | I1 | | | | I2 | |
| | I4 | | | | | | I1 | I3 |
| I5 | I6 | | | | I4 | | I4 | |
| | I6 | | | I5 | | | I5 | |
| | | | | I6 | | | I6 | |
_______ _________ ______
In "Decode", each row has 2 columns. What do First and Second Column mean ?
same as "Write"
And in "Execute, each row has 3 columns. What do First, Second and Third column mean ?
And how is the process ? (The current table is about "In-Order Issue with Out-of-Order Completion").
I've read it many times, in the "Instruction Level Parallelism". But I still don't have any idea about it.
Ferrx - Sunday, December 20, 2015 - link
Aww... Can't do tab-'ing' 0__0