iFixit saved us all a whole lot of trouble and performed a teardown of the new iPad announced last week. The internals were mostly what we expected, down to the Qualcomm MDM9600 LTE baseband. Despite many of the new iPad's specs being a known quantity prior to launch, there were a few surprises in the teardown.
Elpida, like most DRAM manufacturers, does a terrible job of keeping its part number decoders up to date publicly so these two devices (B4064B2MA-8D-F) aren't well documented. The first character in the part number ("B") tells us that we're looking at mobile/low-power DDR2 memory. The next two characters ("40") typically refer to the device density, the 4 in this case likely means 4Gbit while the 0 is a bit odd since it usually refers to DRAM page-size. It's the fourth and fifth characters that are a bit odd to me ("64"). Usually these tell us the width of the DRAM interface, the 64 would imply something that doesn't appear to be true (initial memory bandwidth numbers don't show any increase in memory bandwidth
). It's quite possible that I'm reading the part number incorrectly, so if anyone out there has an updated source on Elpida (and other) DRAM part numbers please do share. Update: The 64 doesn't imply a 64-bit interface as we can see from this datasheet. The two devices are 32-bits wide each, unchanged from A5 implementations. Thanks ltcommanderdata!
As you might have guessed from the fact that Apple now adorns the A5X with a metal heatspreader, Apple has potentially made the shift from a wirebond package to flip-chip. What you're looking at in the shot above with the heatspreader removed is the bottom of the A5X die. If you were to drill down from above you'd see a layer of logic then several metal layers. Moving to a flip-chip BGA package allows for better removal of heat (the active logic is closer to the heatsink), as well as enabling more IO pins/balls on the package itself. Running gold wires from a die to the package quickly becomes a bottleneck as chip complexity increases.
Note that it is possible for Apple to have used flip-chip in the A5 and simply hidden it under the PoP memory stack. Intel's Medfield for example uses a FC-BGA package but will be covered by DRAM in a PoP configuration.
Update: Chipworks has actually measured the A5X die: 162.94mm^2. This means that our visual inspection was inaccurate and Apple is likely still on a 45nm process, which would explain the unchanged CPU clocks. This also helps explain the move away from a PoP stack. At 45nm the A5X's worst case thermals (heavy GPU load) probably demand much better cooling, hence the direct attach heatspreader + thermal paste.
Using the Toshiba eMMC NAND that resides next to the A5X as a reference, we can come up with a rough idea of die size. Based on Toshiba's public documentation, 24nm eMMC 16GB parts measure 12mm x 16mm. Using photoshop and the mystical power of ratios we come up with a rough estimate of 10.8mm x 10.8mm for the A5X die, or 117.5mm^2. If you remember back to our iPad analysis article, we guessed that conservative scaling on a 32nm process would give Apple a ~125mm^2 die for the A5X. While there's a lot of estimation in our methodology, it appears likely that the A5X's die is built on a 28/32nm process - or at least not a 45nm process. Note that this value is entirely dependent on the dimensions of Toshiba's NAND being accurate as well as the photo being as level and distortion-free as possible.
I'll chime in a little later to talk about A5X SoC performance.