AMD's Next-Generation Mobile Architecture Revealed: Griffinby Anand Lal Shimpi on May 18, 2007 12:10 AM EST
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New Memory Controller
Although the underlying architecture of Griffin is K8 based, the memory controller takes a lot of cues from Barcelona/Phenom. There's a new DRAM prefetcher, similar but not identical to what will be in Phenom, but many of the efficiency improvements in the new desktop core will make their way to Griffin as well. Taken from our Barcelona architecture article:
"One strength of Intel's FB-DIMM architecture used in Xeon servers is that you can execute read and write requests to the AMB simultaneously. With standard DDR2 memory, you can do one or the other, and there's a penalty for switching between the two types of operations. If you have a fairly random mixture of reads and writes you can waste a lot of time switching between the two rather than performing all of your reads sequentially then switching over to writes. The K8's memory controller made some allowances for preferring reads over writes since they take less time, but in Barcelona the memory controller is far more intelligent.
Now, instead of executing writes as soon as they show up, writes are stored in a buffer and once the buffer reaches a preset threshold the controller bursts the writes sequentially. What this avoids is the costly read/write switch penalty, helping improve bandwidth efficiency and reduce latency."
AMD did not make it clear whether Griffin also featured two independent 64-bit DDR2 memory controllers or a single 128-bit one. And, of course, as the memory controller is a part of the North Bridge it operates at a separate, lower voltage than the rest of the CPU cores.