As of late, Intel has been unusually guarded about releasing information about its microprocessor designs. Haswell launched last year with great architecture disclosure, but very limited disclosure about die sizes, transistor counts and almost anything surrounding the interface between Haswell and its optional embedded DRAM (Crystalwell) counterpart. This week at ISSCC, Intel will finally be filling in some of the blanks. The first bit of new information we have are official transistor counts for the range of Haswell designs. At launch Intel only disclosed transistor counts and die areas for Haswell ULT GT3 (dual-core, on-die PCH, GT3 graphics) and Haswell GT2 (quad-core, no on-die PCH, GT2 graphics). Today we have both the minimum and maximum configurations for Haswell. Note all transistor counts below are...

Intel at ISSCC '12: More Research into Near Threshold Voltage

At IDF last year Intel's Justin Rattner demonstrated a 32nm test chip based on Intel's original Pentium architecture that could operate near its threshold voltage. The power consumption of...

7 by Anand Lal Shimpi on 2/20/2012

Intel Demonstrates dual-core Atom SoC with Integrated WiFi Transceiver

This week is the annual International Solid-State Circuits Conference (ISSCC) where chip companies from all walks of life present papers documenting everything from shipping architectures to future research projects...

9 by Anand Lal Shimpi on 2/20/2012

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