Intel Xeon E5 Version 3: Up to 18 Haswell EP Cores
by Johan De Gelas on September 8, 2014 12:30 PM ESTSKUs and Pricing
Before we start with the benchmarks, let's first see what you get for your money. To reduce the clutter, we have not listed all of the SKUs but have tried to include useful points of comparison. Also note that we are not comparing pricing or performance with AMD at this point, as AMD has not updated its server CPU offerings for almost 2 years. The Steamroller architecture was very promising and addressed many of the bottlenecks we discovered in the earlier Opteron 6200, but unfortunately it was never made into a high end server CPU. So basically, Intel's only competition right now is the previous generation Xeons, which means Intel has to convince server buyers that upgrading to the latest Xeon pays off.
| Intel Xeon E5 v2 versus v3 2-socket SKU Comparison | |||||||||
| Xeon E5 | Cores/ Threads |
TDP | Clock Speed (GHz) |
Price | Xeon E5 | Cores/ Threads |
TDP | Clock Speed (GHz) |
Price |
| High Performance (20 – 30MB LLC) | High Performance (35-45MB LLC) | ||||||||
| 2699 v3 | 18/36 | 145W | 2.3-3.6 | $4115 | |||||
| 2698 v3 | 16/32 | 135W | 2.3-3.6 | $3226 | |||||
| 2697 v2 | 12/24 | 130W | 2.7-3.5 | $2614 | 2697 v3 | 14/28 | 145W | 2.6-3.6 | $2702 |
| 2695 v2 | 12/24 | 115W | 2.4-3.2 | $2336 | 2695 v3 | 14/28 | 120W | 2.3-3.3 | $2424 |
| "Advanced" (20-30MB LLC) | |||||||||
| 2690 v2 | 10/20 | 130W | 3-3.6 | $2057 | 2690 v3 | 12/24 | 135W | 2.6-3.5 | $2090 |
| 2680 v2 | 10/20 | 115W | 2.8-3.6 | $1723 | 2680 v3 | 12/24 | 120W | 2.5-3.3 | $1745 |
| 2660 v2 | 10/20 | 115W | 2.2-3.0 | $1389 | 2660 v3 | 10/20 | 105W | 2.6-3.3 | $1445 |
| 2650 v2 | 8/16 | 95W | 2.6-3.4 | $1166 | 2650 v3 | 10/20 | 105W | 2.3-3.0 | $1167 |
| Midrange (10 – 20MB LLC) | Midrange (15-25MB LLC) | ||||||||
| 2640 v2 | 8/16 | 95W | 2.0-2.5 | $885 | 2640 v3 | 8/16 | 90W | 2.6-3.4 | $939 |
| 2630 v2 | 6/12 | 80W | 2.6-3.1 | $612 | 2630 v3 | 8/16 | 85W | 2.4-3.2 | $667 |
| Frequency optimized (15 – 25MB LLC) | Frequency optimized (10-20MB LLC) | ||||||||
| 2687W v2 | 8/16 | 150W | 3.4-4.0 | $2108 | 2687W v3 | 10/20 | 160W | 3.1-3.5 | $2141 |
| 2667 v2 | 8/16 | 130W | 3.3-4.0 | $2057 | 2667 v3 | 8/16 | 135W | 3.2-3.6 | $2057 |
| 2643 v2 | 6/12 | 130W | 3.5-3.8 | $1552 | 2643 v3 | 6/12 | 135W | 3.4-3.7 | $1552 |
| 2637 v2 | 4/12 | 130W | 3.5-3.8 | $996 | 2637 v3 | 4/8 | 135W | 3.5-3.7 | $996 |
| Budget (15MB LLC) | Budget (15MB LLC) | ||||||||
| 2609 v2 | 4/4 | 80W | 2.5 | $294 | 2609 v3 | 6/6 | 85W | 1.9 | $306 |
| 2603 v2 | 4/4 | 80W | 1.8 | $202 | 2603 v3 | 6/6 | 85W | 1.6 | $213 |
| Power Optimized (15 – 25MB LLC) | Power Optimized (20-30MB LLC) | ||||||||
| 2650L v2 | 10/20 | 70W | 1.7-2.1 | $1219 | 2650L v3 | 12/24 | 65W | 1.8-2.5 | $1329 |
| 2630L v2 | 6/12 | 70W | 2.4-2.8 | $612 | 2630L v3 | 8/16 | 55W | 1.8-2.9 | $612 |
At the top of the product stack is the new E5-2699 v3, and it's priced accordingly: over $4000 for the most cores Intel has ever put in a Xeon processor. TDP has also gone up compared to the previous generation's top SKU, but for six additional cores that's probably reasonable.
At first glance, the 2695 v3 looks interesting for the performance hungry as it the cheapest "HCC" (High Core Count) option. You get the largest die with the two memory controllers, 35MB LLC, two rings, and TDP is limited to 120W. Of course the question is how well Turbo Boost will compensate for the relatively low base clock.
For those looking for a good balance between price/performance and power, the 2650L v3 offers a 100MHz higher clock, much higher Turbo Boost, two extra cores, and a slightly lower TDP for about $100 more. This SKU looks very tempting for people who do not need the ultimate in processing power, e.g. those looking for a host for their VMs.
Lastly, there is the 2667 v3 which has a high base clock (3.2) and a still reasonable TDP of 135W for all applications that need processing power but do not scale beyond a certain core count.
Those are the SKUs that we have included in this review, so let's see how they fare.
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LostAlone - Saturday, September 20, 2014 - link
Given the difference in size between the two companies it's not really all that surprising though. Intel are ten times AMD's size, and I have to imagine that Intel's chip R&D department budget alone is bigger than the whole of AMD. And that is sad really, because I'm sure most of us were learning our computer science when AMD were setting the world on fire, so it's tough to see our young loves go off the rails. But Intel have the money to spend, and can pursue so many more potential avenues for improvement than AMD and that's what makes the difference.Kevin G - Monday, September 8, 2014 - link
I'm actually surprised they released the 18 core chip for the EP line. In the Ivy Bridge generation, it was the 15 core EX die that was harvested for the 12 core models. I was expecting the same thing here with the 14 core models, though more to do with power binning than raw yields.I guess with the recent TSX errata, Intel is just dumping all of the existing EX dies into the EP socket. That is a good means of clearing inventory of a notably buggy chip. When Haswell-EX formally launches, it'll be of a stepping with the TSX bug resolved.
SanX - Monday, September 8, 2014 - link
You have teased us with the claim that added FMA instructions have double floating point performance. Wow! Is this still possible to do that with FP which are already close to the limit approaching just one clock cycle? This was good review of integer related performance but please combine with Ian to continue with the FP one.JohanAnandtech - Monday, September 8, 2014 - link
Ian is working on his workstation oriented review of the latest XeonKevin G - Monday, September 8, 2014 - link
FMA is common place in many RISC architectures. The reason why we're just seeing it now on x86 is that until recently, the ISA only permitted two registers per operand.Improvements in this area maybe coming down the line even for legacy code. Intel's micro-op fusion has the potential to take an ordinary multiply and add and fuse them into one FMA operation internally. This type of optimization is something I'd like to see in a future architecture (Sky Lake?).
valarauca - Monday, September 8, 2014 - link
The Intel compiler suite I believe already convertsx *= y;
x += z;
into an FMA operation when confronted with them.
Kevin G - Monday, September 8, 2014 - link
That's with source that is going to be compiled. (And don't get me wrong, that's what a compiler should do!)Micro-op fusion works on existing binaries years old so there is no recompile necessary. However, micro-op fusion may not work in all situations depending on the actual instruction stream. (Hypothetically the fusion of a multiply and an add in an instruction stream may have to be adjacent to work but an ancient compiler could have slipped in some other instructions in between them to hide execution latencies as an optimization so it'd never work in that binary.)
DIYEyal - Monday, September 8, 2014 - link
Very interesting read.And I think I found a typo: page 5 (power optimization). It is well known that THE (not needed) Haswell HAS (is/ has been) optimized for low idle power.
vLsL2VnDmWjoTByaVLxb - Monday, September 8, 2014 - link
Colors or labeling for your HPC Power Consumption graph don't seem right.JohanAnandtech - Monday, September 8, 2014 - link
Fixed, thanks for pointing it out.