Justin Rattner kicked off Intel's Spring Developer Forum with a talk about Energy Efficiency, inevitably involving a discussion about Conroe, Merom and Woodcrest.

This slide below is particularly interesting as it is the first time Intel has actually disclosed this sort of information. The chart plots the amount of energy required to execute a single instruction as a function of processor performance. Obviously, the higher the performance, the lower the efficiency.

The next version of the slide includes the work from the Israel Design Center, more specifically the Pentium M and Core Duo.

The Pentium M was actually able to match the energy efficiency of the original Pentium processor. Succeeding generations of the Pentium M continued the trend, offering energy efficiency of the original Pentium while offering performance competitive with the Pentium 4 processor.

Introducing the Core Micro-Architecture
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  • nicolasb - Wednesday, March 08, 2006 - link

    What do I need to do so that anandtech.com will let me see the pictures when I'm reading its articles? :-( Reply
  • stephenbrooks - Sunday, March 12, 2006 - link

    I've found that the pictures load as 1x1 blank GIFs in Opera but appear fine in IE. That really sucks. Reply
  • zephyrprime - Tuesday, March 07, 2006 - link

    Anand says that SSE will execute in a single cycle but I think Intel really meant that SSE will have single cycle throughput, not latency. Notice that in the slide Intel simply writes "single cycle SSE". SSE instructions (except some of the really easy ones) are currently broken down from 128bits -> 2x64bit instructions to actually execute. This has long been the biggest weak point of SSE.

    I expect latency to be 5cycles for SSE FP multiply (it's currently 6). I expect throughput to be 1 cycle for SSE FP multiply (it's currently 2). So instruction throughput will theoretically double.
    Reply
  • Anand Lal Shimpi - Tuesday, March 07, 2006 - link

    You are quite correct, Intel just clarified this point to us and I've updated the article. Thanks for the pointer :)

    Take care,
    Anand
    Reply
  • Hulk - Tuesday, March 07, 2006 - link

    Do all SSE instructions execute in the same number of cycles?

    This crazy projections are always more exciting when they come from Intel because they do have a track record of NOT producing vaporware.

    On the other hand their performance figures are always way optimistic.

    If you look at the middle ground Conroe will probably be a bit faster than X2 per clock cycle. We'll see if they can ramp up the clockspeeds for release...
    Reply
  • Doormat - Tuesday, March 07, 2006 - link

    "While we'll get a better idea of performance of Conroe, Merom and Woodcrest later today, Rattner did whet our appetites"

    Is that a typo or a reference (inside joke?) about performance numbers....
    Reply
  • Rock Hydra - Tuesday, March 07, 2006 - link

    That's the proper use for the word.
    I suppose what he's trying to say is they're satisfied with the info disclosed at the time.
    Reply
  • xtremejack - Tuesday, March 07, 2006 - link

    Whet means sharpen, right. Means becoming eager for more information, I suppose Reply
  • adamfilipo - Tuesday, March 07, 2006 - link

    same here. images arent loading
    hope conroe kicks ass, my next powermac will have it
    Reply
  • DigitalFreak - Tuesday, March 07, 2006 - link

    show me the benchies! Reply

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