Yesterday we published Ivy Bridge's transistor count as 1.48 billion. It turns out that was wrong as Intel's Mooly Eden accidentally read the B in billion as an 8 while on stage. The real number is 1.4 billion. When we published that story we compared it to Intel's Sandy Bridge, which at launch was said to be 995 million transistors. However at IDF Intel had been using another number: 1.16 billion transistors. It turns out both are right, but why is there a difference?

When designing a microprocessor you end up with a schematic of all of the circuits and transistors in the design. With the design schematic done layout is next on the list. However sometimes in the process of moving from the schematic to layout phase, transistor count baloons. The reason is simple. There are some circuits which may be represented by a single transistor at the schematic phase, but for more efficient layout use four transistors in tandem. For Sandy Bridge the 995M number is for the number of transistors in the schematic, while 1.16 billion is how many transistors are put down at the fab. Both are correct, but the 1.16B number is directly comparable to Ivy Bridge's 1.4B transistors.

That puts Ivy Bridge's transistor count at 20.7% higher than Sandy Bridge, which is more in line with what to expect from a tick.

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  • JMS3072 - Thursday, September 15, 2011 - link

    Wouldn't Ivy Bridge's transistor count likewise balloon when it gets laid out at the fab? Reply
  • Sagath - Thursday, September 15, 2011 - link

    Yes, unless the 1.4B count is already the fab count, and not the schematic count. Reply
  • iwodo - Thursday, September 15, 2011 - link

    Arh, that is actually a good question. Also i wonder if Intel are then making more profits from every tick? Since every node you save roughly 45% of die size. i.e Roughly Double the transistor in same die space. Reply
  • JMS3072 - Thursday, September 15, 2011 - link

    I'd imagine so, but they also have to pay R&D to get the node shrunk...which I can't imagine would be cheap. Reply
  • DanNeely - Thursday, September 15, 2011 - link

    Tick dies are always smaller than Tock dies. Initial production volumes for the new process are lower than the mature one (both in number of wafers, and defect rates); so the CPU only sees incremental gains in transistor count. Then as the process matures and a new more complex architecture launches in the Tock the die size jumps back up to roughly the same size as the old Tock. Reply
  • bahamakyle - Friday, September 16, 2011 - link

    'Both are correct, but the 1.16B number is directly comparable to Ivy Bridge's 1.4B transistors.'

    The 1.4B number is already the ballooned fab value.
    Reply
  • jwilliams4200 - Thursday, September 15, 2011 - link

    Why should we expect only 20% more transistors when the lithography size is reduced to 69% of the former size?

    Since the transistors generally scale in both dimensions (i.e., length and width both smaller), I would expect the transistor count to go up by even more than that implied by a 31% reduction in scale. Probably less than double the former transistor count, but not by a lot. Certainly 50% increase does not seem high.

    Of course, things are more complicated with Ivy Bridge, since it will use the new multiple-gate transistors. But I would not expect that to make a big difference.

    Besides, Moore's law for transistor counts says it should double every 18 months. So it seems your "typical 20%" does not make sense from either a geometry standpoint or from the standpoint of Moore's law.
    Reply
  • jwilliams4200 - Thursday, September 15, 2011 - link

    Correction: Moore's law for transistor counts specifies a doubling every two years. But since there is a "tick" every two years, that means a tick should be a double in transistor count if Moore's law still holds. Reply
  • yankeeDDL - Thursday, September 15, 2011 - link

    I believe you may be confusing a few things.
    Going from 28nm to 22nm doesn't require, in principle, any change in the number of transistors.
    So, in theory, Intel could do a die-shrink of SB and port it 1:1 to 22nm with the same exact transistor count (1.16B).
    The fact that the node is smaller, doesn't mean that all transistors are smaller. Power-gating transistors, for example, are usually very large and don't scale with technology.
    However, in a CPU, the majority of the area is occupied by minimum-size logic gates, which shrink directly from 28nm to 22nm.

    It seems though that you're trying to keep the die area constant, which it does not: one of the reasons to go to a smaller node is to be able to have smaller chips, so that the cost-per-transistor is lower. Think about making 1.16B transistors in the 0.18um node, which was used for the Pentium III: the die size would be huge.

    The "typical 20%" comes from the fact that every technology shrink, Intel makes some upgrades to the architecture: maybe a bit more cache, and, in this case, a new GPU core. It is not really related to the % of shrink.
    The Moore's law is also something different, as it refers to the doubling of transistors per unit area, which is approximately kept going down to 22nm.
    Reply
  • jwilliams4200 - Thursday, September 15, 2011 - link

    28nm? What is that? Sandy Bridge is 32nm. Ivy Bridge is 22nm.

    Anyway, not confused, I was asking what basis does he expect a 20% increase. I'm aware the die size usually decreases on a tick.

    I suppose the answer to my question is that he expects 20% on the basis of past ticks being about 20%. But if that is his basis, then it would have been a much better article if he listed the transistor count changes for all previous ticks.
    Reply

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